During programming of a Flash memory cell, it is important to properly set the voltage applied to the various terminals thereof (i.e., gate, source, drain, and body terminals). In the multi-level flash memory field where the cell is programmed at different threshold voltage values, node stability becomes an even more critical problem.
The simple case of programming a multi-level cell with two bits per cell will now be considered, i.e., a two-level cell with four possible combinations of storable logic values. Turning now to FIG. 1, the distributions of four different programming states of such a cell (i.e., the distributions of its possible threshold voltage values), are shown. The programming step of a Flash cell is typically preceded by an erasing step. Consequently, in the beginning the cell is brought to the logic state 11, the state with the lowest threshold.
The programming algorithm may be split into n substantially identical steps. In the first part of each of these steps, the Flash memory cell is biased to keep the drain node at a fixed voltage value (typically +4V), the source node to ground, and the body at a fixed negative value (typically −1.2V). The gate node is initially set at a voltage of 1.5V, and is then increased in subsequent steps, for example, by 300 mV at each further step. This leads to an increase in the cell threshold voltage in steps, as illustrated in FIG. 1.
In the second part of each programming step, the state of the cell is tested through a reading operation (verify). If the cell does not reach the desired distribution, the operation is repeated by increasing the gate voltage. If, on the other hand, the cell threshold voltage reaches the desired distribution, the programming thereof ends.
The programming step typically does not involve only one cell, rather a certain number of cells are programmed in parallel. When one or more cells reach the desired threshold value (i.e., it reaches the desired threshold distribution), they are excluded from the following programming step which continues only for the remaining cells that have yet to reach the predetermined state.
In some fairly recent prior art memory devices, the programming step involves programming about seventy cells in parallel, which results in a variable current load for the drain voltage regulator during the different programming steps. The changes of the threshold voltage and the applied gate voltage cause a different current absorption by the memory cells. Moreover, when the cells have reached the desired state, they are disconnected through a program load transistor, for example, as shown in the schematic circuit diagram of FIG. 2.
It will therefore be understood that the cell drain voltage regulator, in the different programming steps, has to provide a constant voltage value, but in different current load conditions. The drain voltage VPD (+4V) is derived from the band gap reference voltage (VGB) according to the following relation:
            V      PD        =                  V        BG            ·              (                  1          +                                    R              f                                      R              g                                      )              ,which expresses the gain of a feedback voltage amplifier in a non-inverting configuration.
The drain regulator, for layout requirements, may be at a certain distance from the program load transistors PL. The interconnection metal line bringing the adjusted voltage VPD to these transistors, inserts a parasitic resistance, quantifiable in some tens of ohms. Considering that each memory cell can absorb a drain current of about 60 μA, with seventy cells being programmed the total current can reach 4 mA. With a parasitic resistance Rpars for the metal line equal to 25 Ω, as shown in FIG. 3, the voltage drop thereon can reach up to 100 mV. Since the cells which have reached the appropriate distribution are disconnected from the adjusted voltage VPD, the cells upon which programming continues may have a drain voltage changed by +100 mV in some cases.
Some typical curves showing the threshold voltage change in the programming step according to different drain voltage values are schematically represented in FIG. 4. In the illustrated diagram, the abscissa indicates the gate voltage, and the ordinate indicates the threshold voltage. If the drain voltage is constant during all of the programming steps, the cell threshold voltage change follows one of these characteristics. If, on the other hand, the drain voltage changes during programming, the threshold voltage change translates in another characteristic. This results in a higher threshold jump and a widening of the distributions associated with the circuit of FIG. 1 with a corresponding decrease in the reading noise margin or, in the worst case, in real failures due to an excessive distribution widening.